1. Field of the Invention
The present invention relates to reducing jitter in mixed-signal circuitry, for example in digital-to-analog converters (DACs). Such circuitry includes a mixture of digital circuitry and analog circuitry.
2. Description of the Related Art
FIG. 1 of the accompanying drawings shows parts of a conventional DAC of the so-called xe2x80x9ccurrent-steeringxe2x80x9d type. The DAC 1 is designed to convert an mbit digital input word (D1-Dm) into a corresponding analog output signal.
The DAC 1 contains analog circuitry including a plurality (n) of identical current sources 21 to 2n, where n=2mxe2x88x921. Each current source 2 passes a substantially constant current I. The analog circuitry further includes a plurality of differential switching circuits 41, to 4n corresponding respectively to the n current sources 21, to 2n,. Each differential switching circuit 4 is connected to its corresponding current source 2 and switches the current I produced by the current source either to a first terminal, connected to a first connection line A of the converter, or a second terminal connected to a second connection line B of the converter.
Each differential switching circuit 4 receives one of a plurality of digital control signals T1 to Tn (called xe2x80x9cthermometer-coded signalsxe2x80x9d for reasons explained hereinafter) and selects either its first terminal or its second terminal in accordance with the value of the signal concerned. A first output current IA of the DAC 1 is the sum of the respective currents delivered to the differential-switching-circuit first terminals, and a second output current IB of the DAC 1 is the sum of the respective currents delivered to the differential-switching-circuit second terminals.
The analog output signal is the voltage difference VAxe2x88x92VB between a voltage VA produced by sinking the first output current IA of the DAC 1 into a resistance R and a voltage VB produced by sinking the second output current IB of the converter into another resistance R.
In the FIG. 1 DAC the thermometer-coded signals T1 to Tn are derived from the binary input word D1-Dm by digital circuitry including a binary-thermometer decoder 6. The decoder 6 operates as follows.
When the binary input word D1-Dm has the lowest value the thermometer-coded signals T1-Tn are such that each of the differential switching circuits 41 to 4n, selects its second terminal so that all of the current sources 21 to 2nare connected to the second connection line B. In this state, VA=0 and VB=nIR. The analog output signal VAxe2x88x92VB=xe2x88x92nIR.
As the binary input word D1-Dm increases progressively in value, the thermometer-coded signals T1 to Tn produced by the decoder 6 are such that more of the differential switching circuits select their respective first terminals (starting from the differential switching circuit 41) without any differential switching circuit that has already selected its first terminal switching back to its second terminal. When the binary input word D1-Dm has the value i, the first i differential switching circuits 41 to 4i select their respective first terminals, whereas the remaining nxe2x88x92i differential switching circuits 4i+1 to 4nselect their respective second terminals. The analog output signal VAxe2x88x92VB is equal to (2ixe2x88x92n)IR.
FIG. 2 shows an example of the thermometer-coded signals generated for a three-bit binary input word D1-D3 (i.e. in this example m=3). In this case, seven thermometer-coded signals T1 to T7 are required (n=2mxe2x88x92=7).
As FIG. 2 shows, the thermometer-coded signals T1 to Tn generated by the binary-thermometer decoder 6 follow a so-called thermometer code in which it is known that when an rth-order signal Tr is activated (set to xe2x80x9c1xe2x80x9d), all of the lower-order signals T1 to Trxe2x88x921 will also be activated.
Thermometer coding is popular in DACs of the current-steering type because, as the binary input word increases, more current sources are switched to the first connection line A without any current source that is already switched to that line A being switched to the other line B. Accordingly, the input/output characteristic of the DAC is monotonic and the glitch impulse resulting from a change of 1 in the input word is small.
However, when it is desired to operate such a DAC at very high speeds (for example 100 MHz or more), it is found that glitches may occur at one or both of the first and second connection lines A and B, producing a momentary error in the DAC analog output signal VAxe2x88x92VB. These glitches in the analog output signal may be code-dependent and result in harmonic distortion or even non-harmonic spurs in the output spectrum.
Some causes of these glitches have been determined to be as follows.
Firstly, the digital circuitry (the binary-thermometer decoder 6 and other digital circuits) is required to switch very quickly and its gate count is quite high. Accordingly, the current consumption of the digital circuitry could be as much as 20 mA per 100 MHz at high operating speeds. This combination of fast switching and high current consumption inevitably introduces a high degree of noise into the power supply lines. Although it has previously been considered to separate the power supplies for the analog circuitry (e.g. the current sources 21 to 2n and differential switching circuits 41 to 4n in FIG. 1) from the power supplies for the digital circuitry, this measure alone is not found to be wholly satisfactory when the highest performance levels are required. In particular, noise arising from the operation of the binary-thermometer decoder 6 can lead to skew in the timing of the changes in the thermometer-coded signals T1 to Tn in response to different changes in the digital input word D1 to Dm. For example, it is estimated that the skew may be several hundreds of picoseconds. This amount of skew causes significant degradation of the performance of the DAC and, moreover, being data-dependent, the degradation is difficult to predict.
Secondly, in order to reduce the skew problem mentioned above, it may be considered to provide a set of latch circuits, corresponding respectively to the thermometer-coded signals T1 to Tn, between the digital circuitry and the analog circuitry, which latches are activated by a common timing signal such that the outputs thereof change simultaneously. However, surprisingly it is found that this measure alone is not wholly effective in removing skew from the thermometer-coded signals. It is found, for example, that data-dependent jitter still remains at the outputs of the latch circuits and that the worst-case jitter increases in approximate proportion to the number of thermometer-coded signals. Thus, with (say) 64 thermometer-coded signals the worst-case jitter may be as much as 20 picoseconds which, when high performance is demanded, is excessively large.
According to a first aspect of the present invention there is provided mixed-signal circuitry comprising: analog circuitry having an input for receiving a digital control signal and operable to produce one or more analog signals in dependence upon the received digital control signal; and digital circuitry comprising: a main clocked circuit, clocked by an applied clock signal, and having an output connected operatively to said input of the analog circuitry for applying thereto said digital control signal and operable selectively to cause said digital control signal to change at times determined by said clock signal; a dummy clocked circuit, also clocked by said clock signal, which produces a dummy signal at an output thereof and is operable selectively to cause said dummy signal to change at said times; and control circuitry connected with both said clocked circuits and operable at one of said times at which no change occurs in said digital control signal to cause such a change to occur in said dummy signal, and also operable at one of said times at which there is such a change in said digital control signal to prevent such a change from occurring in said dummy signal.
In such mixed-signal circuitry, data-dependent jitter can be reduced significantly.
According to a second aspect of the present invention there is provided digital-to-analog conversion circuitry comprising mixed-signal circuitry which comprises: analog circuitry having an input for receiving a digital control signal and operable to produce one or more analog signals in dependence upon the received digital control signal; and digital circuitry comprising: a main clocked circuit, clocked by an applied clock signal, and having an output connected operatively to said input of the analog circuitry for applying thereto said digital control signal and operable selectively to cause said digital control signal to change at times determined by said clock signal; a dummy clocked circuit, also clocked by said clock signal, which produces a dummy signal at an output thereof and is operable selectively to cause said dummy signal to change at said times; and control circuitry connected with both said clocked circuits and operable at one of said times at which no change occurs in said digital control signal to cause such a change to occur in said dummy signal, and also operable at one of said times at which there is such a change in said digital control signal to prevent such a change from occurring in said dummy signal.
According to a third aspect of the present invention there is provided digital-to-analog conversion circuitry comprising mixed-signal circuitry which comprises: analog circuitry having an input for receiving a digital control signal and operable to produce one or more analog signals in dependence upon the received digital control signal; and digital circuitry comprising: a main clocked circuit, clocked by an applied clock signal, and having an output connected operatively to said input of the analog circuitry for applying thereto said digital control signal and operable selectively to cause said digital control signal to change at times determined by said clock signal; a dummy clocked circuit, also clocked by said clock signal, which produces a dummy signal at an output thereof and is operable selectively to cause said dummy signal to change at said times; and control circuitry connected with both said clocked circuits and operable at one of said times at which no change occurs in said digital control signal to cause such a change to occur in said dummy signal, and also operable at one of said times at which there is such a change in said digital control signal to prevent such a change from occurring in said dummy signal, wherein: said analog circuitry has a plurality of such inputs for receiving respective such digital control signals and is operable to produce its said one or more analog signals in dependence upon the received digital control signals; said digital circuitry comprises a pair of clocked circuits for each said input of the analog circuitry, one clocked circuit of said pair being such a main clocked circuit and the other clocked circuit of the pair being such a dummy clocked circuit; said main clocked circuit of each pair is clocked by said clock signal, and has an output connected operatively to one of said inputs of said analog circuitry for applying one of said digital control signals thereto, and is operable selectively to cause that digital control signal to change at said times; said dummy clocked element of each pair is also clocked by the clock signal, and serves to produce a dummy signal at an output thereof, and is operable selectively to cause that dummy signal to change at said times; and said control circuitry is connected with both clocked circuits of each pair and are operable at one of said times at which no change occurs in said digital control signal of the pair to cause such a change to occur in said dummy signal of the pair, and are also operable at one of said times at which there is such a change in said digital control signal of the pair to prevent such a change from occurring in said dummy signal of the pair, and wherein said analog circuitry comprises a plurality of circuitry segments corresponding respectively to said inputs of the analog circuitry, each segment comprising a current source or current sink circuit, and the or each said analog signal is derived by summing the respective currents sourced, or sunk as the case may be, by the current source/sink circuits of selected ones of said circuitry segments of the analog circuitry, the selection of the circuitry segments being determined by said digital control signals.